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| description the 7544 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 7544 group has a serial i/o, 8-bit timers, a 16-bit timer, and an a/d converter, and is useful for control of home electric appli- ances and office automation equipment. features basic machine-language instructions ...................................... 71 the minimum instruction execution time ......................... 0.25 ? (at 8 mhz oscillation frequency, double-speed mode for the shortest instruction) memory size rom ......................................................... 8 k bytes ram ........................................................ 256 bytes programmable i/o ports ........................................................... 25 interrupts ................................................. 12 sources, 12 vectors timers ............................................................................. 8-bit ? 2 ...................................................................................... 16-bit ? 1 serial i/o ...................... 8-bit ? 1 (uart or clock-synchronized) a/d converter ................................................. 8-bit ? 6 channels clock generating circuit ............................................. built-in type (low-power dissipation by an on-chip oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscilla- tor permitting rc oscillation) watchdog timer ............................................................ 16-bit ? 1 power source voltage x in oscillation frequency at ceramic/quartz-crystal oscillation, in double-speed mode at 8 mhz .................................................................... 4.5 to 5.5 v x in oscillation frequency at ceramic/quartz-crystal oscillation, in high-speed mode at 8 mhz .................................................................... 4.0 to 5.5 v x in oscillation frequency at rc oscillation at 4 mhz .................................................................... 4.0 to 5.5 v power dissipation ........................................... 22.5mw(standard) operating temperature range ................................... ? 0 to 85 ? application office automation equipment, factory automation equipment, home electric appliances, consumer electronics, etc. pin configuration (top view) fig. 1 pin configuration (32p4b type) package type : 32p4b p1 2 /s clk m37544m2-xxxsp m37544g2sp 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p1 3 /s rdy p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref cnv ss v cc x in x out v ss reset p1 1 /t x d p1 0 /r x d p0 7 (led 7 ) p0 6 (led 6 ) p0 5 (led 5 ) p0 4 (led 4 ) p0 3 (led 3 )/tx out p0 2 (led 2 ) p0 1 (led 1 ) p0 0 (led 0 )/cntr 1 p3 4 (led 12 )/int 1 p3 3 (led 11 ) p3 2 (led 10 ) p3 1 (led 9 ) p3 0 (led 8 ) p3 7 (led 13 )/int 0 rev.1.04 2004.06.08 page 1 of 66 rej03b0012-0104z rej03b0012-0104z rev.1.04 2004.06.08 7544 group single-chip 8-bit cmos microcomputer
7544 group rev.1.04 2004.06.08 page 2 of 66 rej03b0012-0104z fig. 3 pin configuration (42s1m type) fig. 2 pin configuration (32p6u-a type) package type : 32p6u-a 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 8 7 6 5 3 4 v cc cnv ss p2 2 /an 2 p0 5 (led 5 ) p0 2 (led 2 ) p0 4 (led 4 ) p0 3 (le d3 )/tx out p0 6 (led 6 ) p0 1 (led 1 ) p0 0 (led 0 )/cntr 1 p3 7 (led 13 )/int 0 M37544M2-XXXGP m37544g2gp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref reset 1 2 p2 0 / an 0 p2 1 / an 1 p1 4 /cntr 0 p1 3 /s rdy p1 2 /s clk p1 1 /t x d p1 0 /r x d p0 7 (led 7 ) x out x in v ss p3 0 (led 8 ) p3 1 (led 9 ) p3 2 (led 10 ) p3 3 (led 11 ) p3 4 (led 12 )/int 1 24 23 22 21 20 19 18 17 package type: 42s1m p0 0 (led 0 )/cntr 1 cnv ss x out x in v ss p0 1 (led 1 ) p0 2 (led 2 ) p0 3 (led 3 )/tx out p0 4 (led 4 ) p3 0 (led 8 ) vcc v ref p0 5 (led 5 ) p1 2 /s clk p2 5 /an 5 p1 4 /cntr 0 nc p2 2 /an 2 nc p2 1 /an 1 p2 0 /an 0 p3 1 (led 9 ) nc p2 3 /an 3 p2 4 /an 4 p0 6 (led 6 ) p0 7 (led 7 ) p3 7 (led 13 )/int 0 reset nc nc p3 4 (led 12 )/int 1 p3 3 (led 11 ) p3 2 (led 10 ) nc p1 0 /r x d p1 1 /t x d nc nc p1 3 /s rdy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 m37544rss nc nc 7544 group rev.1.04 2004.06.08 page 3 of 66 rej03b0012-0104z fig. 4 pin configuration (36pjw-a type) p0 7 (led 7 ) p1 0 /rxd p1 1 /txd p1 2 /s clk p1 3 /s rdy p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 [n.c.] p3 3 (led 11 ) p3 2 (led 10 ) p3 1 (led 9 ) p3 0 (led 8 ) vss x out x in [n.c.] vcc cnvss reset p0 6 (led 6 ) p3 4 (led 12 )/int 1 m37544m2-xxxhp m37544g2hp (note) p2 5 /an 5 v ref 36 [n.c.] [n.c.] p2 4 /an 4 p2 3 /an 3 p2 2 /an 2 p0 5 (led 5 ) p0 4 (led 4 ) p0 3 (led 3 )/tx out p0 2 (led 2 ) p0 1 (led 1 ) p0 0 (led 0 )/cntr 1 p3 7 (led 13 )/int 0 27 26 25 20 19 21 24 23 22 9 8 7 6 5 3 14 2 31 30 29 28 35 34 33 32 10 11 12 13 14 15 16 17 18 n.c.: non connection note: only es version (mp: no plan) package type: 36pjw-a 7544 group rev.1.04 2004.06.08 page 4 of 66 rej03b0012-0104z functional block fig. 5 functional block diagram (32p4b package) functional block diagram (package: 32p4b) 16 11 13 12 p1(5) 31 31 2 32 5 4 p2(6) p3(6) 17 20 18 10 14 15 9 7 8 6 0 19 21 22 p0(8) 30 28 26 24 29 27 25 23 a/d converter (8) x in out x cpu v ss reset v cc cnv ss i/o port p2 i/o port p0 i/o port p1 i/o port p3 si/o(8) ram rom a x y s pc h pc l ps reset input clock generating circuit clock input clock output v ref watchdog timer reset int 0 cntr 0 timer x (8) key-on wakeup prescaler x (8) cntr 1 timer a (16) timer 1 (8) prescaler 1 (8) tx out int 1 7544 group rev.1.04 2004.06.08 page 5 of 66 rej03b0012-0104z fig. 6 functional block diagram (32p6u package) functional block diagram (package: 32p6u) x in ou t x si/o(8) ram rom cpu a x y s pc h pc l ps v ss 11 reset 6 v cc 8 7 cnv ss p1(5) 30 28 26 29 27 32 31 p2(6) p3(6) 12 15 13 5 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 9 10 4 2 3 1 a/d converter (8) v ref watchdog timer reset 0 14 int 0 16 17 cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) cntr 1 timer a (16) p0(8) 25 23 21 19 24 22 20 18 timer 1 (8) prescaler 1 (8) tx out int 1 7544 group rev.1.04 2004.06.08 page 6 of 66 rej03b0012-0104z fig. 7 functional block diagram (36pjw package) functional block diagram (package: 36pjw) x in out x si/ o(8) r a m r o m c p u a x y s pc h pc l ps v ss 13 reset 6 v cc 8 7 cnv ss p1(5) 34 32 30 33 31 36 35 p2 (6) p3 (6) 14 17 15 5 11 12 4 2 3 1 v ref 0 16 int 0 20 21 cntr 0 cntr 1 p0(8) 29 27 25 23 28 26 24 22 tx ou t int 1 a/d converter (8) i/o port p2 i/o port p0 i/o port i/o port p3 reset input clock generating circuit clock input clock output watchdog timer reset timer x (8) key-on wakeup prescaler x (8) timer a (16) timer 1 (8) prescaler 1 (8) 7544 group rev.1.04 2004.06.08 page 7 of 66 rej03b0012-0104z pin description table 1 pin description function ?pply voltage of 4.0 to 5.5 v to vcc, and 0 v to vss. ?eference voltage input pin for a/d converter ?hip operating mode control pin, which is always connected to vss. ?eset input pin for active ? ?nput and output pins for main clock generating circuit ?onnect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins. ?or using rc oscillator, short between the x in and x out pins, and connect the capacitor and resistor. ?f an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?when the on-chip oscillator is selected as the main clock, connect x in pin to v cc and leave x out open. function expect a port function name power source analog reference voltage cnvss reset input clock input i/o port p0 i/o port p1 pin vcc, vss v ref cnvss ______ reset x in p0 0 /cntr 1 p0 1 p0 2 p0 3 /tx out p0 4 ?0 7 ?key-input (key-on wake up interrupt input) pins ?timer x and timer a function pin ?-bit i/o port. ?/o direction register allows each pin to be individually pro- grammed as either input or output. ?mos compatible input level ?mos 3-state output structure ?0 can output a large current for driving led. ?hether a built-in pull-up resistor is to be used or not can be de- termined by program. ?-bit i/o port ?/o direction register allows each pin to be individually pro- grammed as either input or output. ?mos compatible input level ?mos 3-state output structure ?mos/ttl level can be switched for p1 0 and p1 2 ?-bit i/o port having almost the same function as p0 ?mos compatible input level ?mos 3-state output structure p1 0 /rxd p1 1 /txd p1 2 /s clk ____ p1 3 /s rdy p1 4 /cntr 0 p2 0 /an 0 ?2 5 /an 5 p3 0 ?3 3 p3 4 /int 1 p3 7 /int 0 i/o port p2 i/o port p3 ?serial i/o function pin ?timer x function pin ?input pins for a/d converter ?interrupt input pins ?-bit i/o port ?/o direction register allows each pin to be individually programmed as either input or output. ?mos compatible input level (cmos/ttl level can be switched for p3 4 and p3 7 ). ?mos 3-state output structure ?3 can output a large current for driving led. x out clock output ?hether a built-in pull-up resistor is to be used or not can be de- termined by program. 7544 group rev.1.04 2004.06.08 page 8 of 66 rej03b0012-0104z group expansion we are planning to expand the 7544 group as follow: memory type support for mask rom version, one time prom version, and emulator mcu . memory size rom/prom size .............................................................. 8 k bytes ram size ......................................................................... 256 bytes package 32p4b .................................................. 32-pin plastic molded sdip 32p6u-a ...................... 0.8 mm-pitch 32-pin plastic molded lqfp 36pjw-a ...................... 0.5 mm-pitch 36-pin plastic molded ssop 42s1m .................................... 42-pin shrink ceramic piggy back fig. 8 memory expansion plan rom size (bytes) ram size (bytes) 256 8k 0 m37544g2 m37544m2 currently supported products are listed below. table 2 list of supported products part number (p) rom size (bytes) rom size for user () 8192 (8062) ram size (bytes) 256 256 package 32p4b 32p6u-a 36pjw-a 32p4b 32p6u-a 36pjw-a 42s1m remarks mask rom version mask rom version mask rom version one time prom version (blank) one time prom version (blank) one time prom version (blank) emulator mcu m37544m2-xxxsp M37544M2-XXXGP m37544m2-xxxhp m37544g2sp m37544g2gp m37544g2hp (note) m37544rss note: only es version (mp: no plan) 7544 group rev.1.04 2004.06.08 page 9 of 66 rej03b0012-0104z functional description central processing unit (cpu) the mcu uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine-language instructions or the series 740 7544 group rev.1.04 2004.06.08 page 10 of 66 rej03b0012-0104z table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 10 register push and pop at interrupt generation and subroutine call execute jsr on-going routine m (s) (pc h ) (s) (s ?1) m (s) (pc l ) execute rts (pc l ) m (s) (s) (s ?1) (s) (s + 1) (s) (s + 1) (pc h ) m (s) subroutine restore return address s tore return address o n stack m (s) (ps) execute rti (ps) m (s) (s) (s ?1) (s) (s + 1) interrupt service routine restore contents of processor status register m (s) (pc h ) (s) (s ?1) m (s) (pc l ) (s) (s ?1) (pc l ) m (s) (s) (s + 1) (s) (s + 1) (pc h ) m (s) restore return address i flag ??to ?? fetch the jump vector store return address on stack store contents of processor status register on stack interrupt request (note) note : the condition to enable the interrupt interrupt enable bit is ? interrupt disable flag is ? 7544 group rev.1.04 2004.06.08 page 11 of 66 rej03b0012-0104z processor status register (ps) the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to ?? but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. (2) zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is ?? and cleared if the result is anything other than ?? (3) interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is ?? when an interrupt occurs, this flag is automatically set to ??to prevent other interrupts from interfering until the current interrupt is serviced. (4) decimal mode flag (d) the d flag determines whether additions and subtractions are ex- ecuted in binary or decimal. binary arithmetic is executed when this flag is ?? decimal arithmetic is executed when it is ?? decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. (5) break flag (b) the b flag is used to indicate that the current interrupt was gener- ated by the brk instruction. the brk flag in the processor status register is always ?? when the brk instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to ?? the saved processor status is the only place where the break flag is ever set. (6) index x mode flag (t) when the t flag is ?? arithmetic operations are performed be- tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. when the t flag is ?? direct arithmetic operations and direct data trans- fers are enabled between memory locations, i.e. between memory and memory, memory and i/o, and i/o and i/o. in this case, the result of an arithmetic operation performed on data in memory lo- cation 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal ad- dressing modes. (7) overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. (8) negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag 7544 group rev.1.04 2004.06.08 page 12 of 66 rej03b0012-0104z [cpu mode register] cpum the cpu mode register contains the stack page selection bit. this register is allocated at address 003b 16 . switching method of cpu mode register switch the cpu mode register (cpum) at the head of program af- ter releasing reset in the following method. fig. 12 switching method of cpu mode register fig. 11 structure of cpu mode register processor mode bits (note 1) b1 b0 0 0 single-chip mode 0 1 1 0 1 1 not available b7 b0 2: these bits are used only when a ceramic /quartz-crystal oscillation is selected. note 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu ?37544rss?) do not use these when an rc oscillation is selected. oscillation mode selection bit (note 1) 0 : ceramic/quartz-crystal oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( ) = f(x in )/2 (high-speed mode) 0 1 : f( ) = f(x in )/8 (middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f( ) = f(x in ) (double-speed mode)(note 2) on-chip oscillator oscillation control bit 0 : on-chip oscillator oscillation enabled 1 : on-chip oscillator oscillation stop x in oscillation control bit 0 : ceramic/quartz-crystal or rc oscillation enabled 1 : ceramic/quartz-crystal or rc oscillation stop after releasing reset switch the oscillation mode selection bit (bit 5 of cpum) switch the clock division ratio selection bits (bits 6 and 7 of cpum) main routine start with an on-chip oscillator an initial value is set as a ceramic/quartz-crystal oscillation mode. when it is switched to an rc oscillation, its oscillation starts. select 1/1, 1/2, 1/8 or on-chip oscillator. wait by on-chip oscillator operation until establishment of oscillator clock when using a ceramic/quartz-crystal oscillation, wait until establlishment of oscillation from oscillation start s. when using an rc oscillation, wait time is not require d basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). 7544 group rev.1.04 2004.06.08 page 13 of 66 rej03b0012-0104z memory special function register (sfr) area the sfr area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for a stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. note on use the content of ram is undefined when the microcomputer is re- set. the initial values must be surely set before you use it. fig. 13 memory map diagram 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 256 xxxx 16 013f 16 8192 e000 16 e080 16 yyyy 16 zzzz 16 ram rom reserved area sfr area disable interrupt vector area rom area reserved rom area (128 bytes) zero page special pag e ram area ram capacity (bytes) address xxxx 16 rom capacity (bytes) address yyyy 16 reserved rom area address zzzz 16 7544 group rev.1.04 2004.06.08 page 14 of 66 rej03b0012-0104z fig. 14 memory map of special function register (sfr) 0 000 16 0 001 16 0 002 16 0 003 16 0 004 16 0 005 16 0 006 16 0 007 16 0 008 16 0 009 16 0 00a 16 0 00b 16 0 00c 16 0 00d 16 0 00e 16 0 00f 16 0 010 16 0 011 16 0 012 16 0 013 16 0 014 16 0 015 16 0 016 16 0 017 16 0 018 16 0 019 16 0 01a 16 0 01b 16 0 01c 16 0 01d 16 0 01e 16 0 01f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) transmit/receive buffer register (tb/rb) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) baud rate generator (brg) port p1p3 control register (p1p3c) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register1 (tcss1) a/d register (ad) prescaler 1 (pre1) timer 1 (t1) reserved timer x mode register (txm) prescaler x (prex) timer x (tx) reserved reserved a/d control register (adcon) reserved misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) timer a mode register (tam) timer a (low-order) (tal) timer a (high-order) (tah) reserved reserved reserved reserved reserved reserved reserved reserved interrupt request register 2 (ireq2) interrupt control register 2 (icon2) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved timer count source set register2 (tcss2) reserved reserved reserved note : do not access to the sfr area including nothing. 7544 group rev.1.04 2004.06.08 page 15 of 66 rej03b0012-0104z i/o ports [direction registers] pid the i/o ports have direction registers which determine the input/ output direction of each pin. each bit in a direction register corre- sponds to one pin, and each pin can be set to be input or output. when ??is set to the bit corresponding to a pin, this pin becomes an output port. when ??is set to the bit, the pin becomes an in- put port. when data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. pins set to input are float- ing, and permit reading pin values. if a pin set to input is written to, only the port latch is written to and the pin remains floating. [pull-up control register] pull by setting the pull-up control register (address 0016 16 ), ports p0 and p3 can exert pull-up control by program. however, pins set to output are disconnected from this control and cannot exert pull-up control. [port p1p3 control register] p1p3c by setting the port p1p3 control register (address 0017 16 ), a cmos input level or a ttl input level can be selected for ports p1 0 , p1 2 , p3 4 , and p3 7 by program. fig. 16 structure of port p1p3 control register fig. 15 structure of pull-up control register pull-up control register (pull: address 0016 16 , initial value: 00 16 ) p0 0 pull-up control bit p0 1 pull-up control bit p0 2 , p0 3 pull-up control bit p0 4 ?p0 7 pull-up control bit p3 0 ?p3 3 pull-up control bit p3 4 pull-up control bit disable p3 7 pull-up control bit b7 b0 0 : pull-up off 1 : pull-up on n ote : pins set to output ports are disconnected from pull-up control. port p1p3 control register (p1p3c: address 0017 16 , initial value: 00 16 ) b7 b0 p3 7 /int 0 input level selection bit 0 : cmos level 1 : ttl level p3 4 /int 1 input level selection bit 0 : cmos level 1 : ttl level p1 0 ,p1 2 input level selection bit 0 : cmos level 1 : ttl level disable 7544 group rev.1.04 2004.06.08 page 16 of 66 rej03b0012-0104z table 5 i/o port function table pin p0 0 /cntr 1 p0 1 p0 2 p0 3 /tx out p0 4 ?0 7 p1 0 /rxd p1 1 /txd p1 2 /s clk ____ p1 3 /s rdy p1 4 /cntr 0 p2 0 /an 0 p2 5 /an 5 p3 0 ?3 3 p3 4 /int 1 p3 7 /int 0 input/output i/o individual bits i/o format ?mos compatible input level ?mos 3-state output ( note ) non-port function key input interrupt timer x function output timer a function input serial i/o function input/output timer x function input/output a/d conversion input external interrupt input related sfrs pull-up control register timer x mode register timer a mode register interrupt edge selection register serial i/o control register port p1,p3 control register timer x mode register a/d control register pull-up control register interrupt edge selection register pull-up control register port p1,p3 control register diagram no. (1) (2) (3) (4) (5) (6) (7) note : ports p1 0 , p1 2 , p3 4 , and p3 7 are cmos/ttl level. name i/o port p0 i/o port p1 i/o port p2 i/o port p3 (8) (9) (10) (11) 7544 group rev.1.04 2004.06.08 page 17 of 66 rej03b0012-0104z fig. 17 block diagram of ports (1) (6)port p1 2 serial i/o clock output serial i/o mode selection bit serial i/o enable bit serial i/o enable bit serial i/o synchronous clock selection bit direction register data bus port latch serial i/o clock input p1 0 , p1 2 input level selection bit * (2)ports p0 1 ,p0 2 ,p0 4 p0 7 direction register data bus port latch pull-up control to key input interrupt generating circuit (1)port p0 0 direction register data bus port latch pull-up control to key input interrupt generating circuit cntr 1 interrupt input ( 3)port p0 3 direction register data bus port latch pull-up control to key input interrupt generating circuit timer output p0 3 /tx out output valid ( 5)port p1 1 data bus port latch serial i/o output p1 1 /t x d p-channel output disable bit direction register serial i/o enable bit transmit enable bit (4)port p1 0 direction register data bus port latch serial i/o enable bit receive enable bit serial i/o input p1 0 , p1 2 input level selection bit * * p1 0 , p1 2 , p3 4 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. when the ttl level is selected, there is no hysteresis characteristics. p0 0 key-on wakeup selection bit 7544 group rev.1.04 2004.06.08 page 18 of 66 rej03b0012-0104z fig. 18 block diagram of ports (2) pull-up control int interrupt input p3 input level selection bit (10) ports p3 0 ?3 3 pull-up control (8) port p1 4 data bus serial i/o ready output port latch direction register cntr 0 interrupt input pulse output mode timer output serial i/o mode selection bit serial i/o enable bit s rdy output enable bit p1 0 , p1 2 , p3 4 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. when the ttl level is selected, there is no hysteresis characteristics. data bus port latch direction register data bus port latch direction register data bus port latch direction register a/d converter input analog input pin selection bit (11) ports p3 4 , p3 7 data bus port latch direction register * * ( 9) ports p2 0 ?2 5 (7) port p1 3 7544 group rev.1.04 2004.06.08 page 19 of 66 rej03b0012-0104z interrupts interrupts occur by 12 different sources : 5 external sources, 6 in- ternal sources and 1 software source. interrupt control all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. when the interrupt enable bit and the in- terrupt request bit are set to ??and the interrupt disable flag is set to ?? an interrupt is accepted. the interrupt request bit can be cleared by program but not be set. the interrupt enable bit can be set and cleared by program. the reset and brk instruction interrupt can never be disabled with any flag or bit. all interrupts except these are disabled when the interrupt disable flag is set. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. [interrupt edge selection register] intedge the valid edge of external interrupt int 0 and int 1 can be selected by the interrupt edge selection bit, respectively. by the key-on wakeup selection bit, enable/disable of a key-on wakeup of p0 0 pin can be selected. notes on use when setting the followings, the interrupt request bit may be set to ?? ?hen setting external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer x mode register (address 2b 16 ) timer a mode register (address 1d 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge select bit (active edge switch bit) to ?? ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). table 6 interrupt vector address and priority vector addresses ( note 1 ) high-order priority low-order interrupt request generating conditions remarks interrupt source fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 note 1: vector addressed contain internal jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling) external interrupt (active edge selectable) external interrupt (active edge selectable) stp release timer underflow non-maskable software interrupt at reset input at completion of serial i/o data receive at completion of serial i/o transmit shift or when transmit buffer is empty at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at falling of conjunction of input logical level for port p0 (at input) at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer x underflow not available not available at timer a underflow not available at completion of a/d conversion at timer 1 underflow not available at brk instruction execution 1 2 3 4 5 6 7 8 9 10 11 12 13 reset ( note 2 ) serial i/o receive serial i/o transmit int 0 int 1 key-on wake-up cntr 0 cntr 1 timer x reserved area reserved area timer a reserved area a/d conversion timer 1 reserved area brk instruction 7544 group rev.1.04 2004.06.08 page 20 of 66 rej03b0012-0104z fig. 19 interrupt control fig. 20 structure of interrupt-related registers interrupt disable flag i interrupt reque st interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 interrupt edge selection bit (intedge : address 003a 16 , initial value : 00 16 ) interrupt request register 1 serial i/o receive interrupt request bit 0 : no interrupt request issue d 1 : interrupt request issued (ireq1 : address 003c 16 , initial value : 00 16 ) b7 b0 interrupt control register 1 serial i/o receive interrupt enable bit 0 : interrupts disabled 1 : interrupts enabled (icon1 : address 003e 16 , initial value : 00 16 ) interrupt request register 2 disable (returns ??when read) 0 : no interrupt request issue d 1 : interrupt request issued (ireq2 : address 003d 16 , initial value : 00 16 ) b7 b0 interrupt control register 2 disable (returns ??when read) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 , initial value : 00 16 ) (do not write ??to this bit) disable (returns ??when read) timer 1 interrupt enable bit a/d conversion interrupt enable bit disable (returns ??when read) timer a interrupt enable bit disable (returns ??when read) timer x interrupt enable bit cntr 1 interrupt enable bit cntr 0 interrupt enable bit key-on wake up interrupt enable bit int 1 interrupt enable bit int 0 interrupt enable bit serial i/o transmit interrupt enable bit disable (returns ??when read) timer 1 interrupt request bit a/d conversion interrupt request bit disable (returns ??when read) timer a interrupt request bit disable (returns ??when read) timer x interrupt request bit cntr 1 interrupt request bit cntr 0 interrupt request bit key-on wake up interrupt request bit int 1 interrupt request bit int 0 interrupt request bit serial i/o transmit interrupt request bit 1 : key-on wakeup disabled 0 : key-on wakeup enabled p0 0 key-on wakeup enable bit disable (returns ??when read) 1 : rising edge active 0 : falling edge active int 1 interrupt edge selection bit 1 : rising edge active 0 : falling edge active 7544 group rev.1.04 2004.06.08 page 21 of 66 rej03b0012-0104z key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying ? level to any pin of port p0 that has been set to input mode. in other words, it is generated when the and of input level goes from ??to ?? an example of using a key input interrupt is shown in figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports p0 0 to p0 3 as input ports. fig. 21 connection example when using key input interrupt and port p0 block diagram port pxx ??level output pull register bit 3 = ?? port p0 7 latch port p0 7 direction register = ? ** * p0 7 output key input interrupt request port p0 input read circuit * p-channel transistor for pull-up ** cmos output buffer pull register bit 3 = ?? port p0 6 latch port p0 6 direction register = ? ** * p0 6 output pull register bit 3 = ?? port p0 5 latch port p0 5 direction register = ? ** * p0 5 output pull register bit 3 = ?? port p0 4 latch port p0 4 direction register = ? ** * p0 4 output pull register bit 2 = ?? port p0 3 latch port p0 3 direction register = ? ** * p0 3 input pull register bit 2 = ?? port p0 2 latch port p0 2 direction register = ? ** * p0 2 input pull register bit 1 = ?? port p0 1 latch port p0 1 direction register = ? ** * p0 1 input pull register bit 0 = ?? port p0 0 latch port p0 0 direction register = ? ** * p0 0 input falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection port p0 0 key-on wakeup selection bit 7544 group rev.1.04 2004.06.08 page 22 of 66 rej03b0012-0104z timers the 7544 group has 3 timers: timer 1, timer a and timer x. the division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. all the timers are down count timers. when a timer reaches ?? an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to each timer is set to ?? timer 1 timer 1 is an 8-bit timer and counts the prescaler output. when timer 1 underflows, the timer 1 interrupt request bit is set to ?? prescaler 1 is an 8-bit prescaler and counts the signal selected by the timer 1 count source selection bit. prescaler 1 and timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. the value of prescaler 1 latch is set to prescaler 1 when prescaler 1 underflows. the value of timer 1 latch is set to timer 1 when timer 1 underflows. when writing to prescaler 1 (pre1) is executed, the value is writ- ten to both the prescaler 1 latch and prescaler 1. when writing to timer 1 (t1) is executed, the value is written to both the timer 1 latch and timer 1. when reading from prescaler 1 (pre1) and timer 1 (t1) is ex- ecuted, each count value is read out. timer 1 always operates in the timer mode. prescaler 1 counts the signal selected by the timer 1 count source selection bit. each time the count clock is input, the contents of prescaler 1 is decremented by 1. when the contents of prescaler 1 reach ?0 16 ? an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into prescaler 1 and count contin- ues. the division ratio of prescaler 1 is 1/(n+1) provided that the value of prescaler 1 is n. the contents of timer 1 is decremented by 1 each time the under- flow signal of prescaler 1 is input. when the contents of timer 1 reach ?0 16 ? an underflow occurs at the next count clock, and the timer 1 latch is reloaded into timer 1 and count continues. the di- vision ratio of timer 1 is 1/(m+1) provided that the value of timer 1 is m. accordingly, the division ratio of prescaler 1 and timer 1 is 1/((n+1) ? (m+1)) provided that the value of prescaler 1 is n and the value of timer 1 is m. timer 1 cannot stop counting by software. timer a timer a is a 16-bit timer and counts the signal selected by the timer a count source selection bit. when timer a underflows, the timer a interrupt request bit is set to ?? timer a consists of the low-order of timer a (tal) and the high-or- der of timer a (tah). timer a has the timer a latch to retain the reload value. the value of timer a latch is set to timer a at the timing shown below. ?when timer a undeflows. ?when an active edge is input from cntr 1 pin (valid only when period measurement mode and pulse width hl continuously mea- surement mode). when writing to both the low-order of timer a (tal) and the high- order of timer a (tah) is executed, the value is written to both the timer a latch and timer a. when reading from the low-order of timer a (tal) and the high-or- der of timer a (tah) is executed, the following values are read out according to the operating mode. ?in timer mode, event counter mode: the count value of timer a is read out. ?in period measurement mode, pulse width hl continuously mea- surement mode: the measured value is read out. be sure to write to/read out the low-order of timer a (tal) and the high-order of timer a (tah) in the following order; read read the high-order of timer a (tah) first, and the low-order of timer a (tal) next and be sure to read out both tah and tal. write write to the low-order of timer a (tal) first, and the high-order of timer a (tah) next and be sure to write to both tal and tah. timer a can be selected in one of 4 operating modes by setting the timer a mode register. (1) timer mode timer a counts the selected by the timer a count source selection bit. each time the count clock is input, the contents of timer a is decremented by 1. when the contents of timer a reach ?000 16 ? an underflow occurs at the next count clock, and the timer a latch is reloaded into timer a. the division ratio of timer a is 1/(n+1) provided that the value of timer a is n. (2) period measurement mode in the period measurement mode, the pulse period input from the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in the timer a latch is reloaded in timer a and count continues. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit .the count value when trigger input from cntr 1 pin is accepted is retained until timer a is read once. 7544 group rev.1.04 2004.06.08 page 23 of 66 rej03b0012-0104z (3) event counter mode timer a counts signals input from the p0 0 /cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit . (4) pulse width hl continuously measurement mode in the pulse width hl continuously measurement mode, the pulse width (??and ??levels) input to the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. the count value when trigger input from the cntr 1 pin is ac- cepted is retained until timer a is read once. timer a can stop counting by setting ??to the timer a count stop bit in any mode. also, when timer a underflows, the timer a interrupt request bit is set to ?? note on timer a is described below; note on timer a cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. when this bit is ?? the cntr 1 interrupt request bit is set to ??at the falling edge of the cntr 1 pin input signal. when this bit is ?? the cntr 1 interrupt request bit is set to ??at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 22 structure of timer a mode register fig. 23 timer count source set register 2 timer a mode register (tam : address 001d 16 , initial value: 00 16 ) b7 b0 disable (return ??when read) timer a operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer a count stop bit 0 : count start 1 : count stop timer count source set register 2 (tcss2 : address 002f 16 , initial value: 00 16 ) b7 b0 timer 1 count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : on-chip oscillator output 1 1 : disable note : system operates using an on-chip oscillator as a count source by setting the on-chip oscillator to oscillation enabled by bit 3 of cpum. disable (return ??when read) timer a count source selection bits b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : on-chip oscillator output 1 1 : disable 7544 group rev.1.04 2004.06.08 page 24 of 66 rej03b0012-0104z (4) pulse width measurement mode in the pulse width measurement mode, the pulse width of the sig- nal input to p1 4 /cntr 0 pin is measured. the operation of timer x can be controlled by the level of the sig- nal input from the cntr 0 pin. when the cntr 0 active edge switch bit is ?? the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is ?? the count is stopped while the pin is ?? also, when the cntr 0 active edge switch bit is ?? the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is ?? the count is stopped while the pin is ?? timer x can stop counting by setting ??to the timer x count stop bit in any mode. also, when timer x underflows, the timer x interrupt request bit is set to ?? note on timer x is described below; note on timer x cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. timer x timer x is an 8-bit timer and counts the prescaler x output. when timer x underflows, the timer x interrupt request bit is set to ?? prescaler x is an 8-bit prescaler and counts the signal selected by the timer x count source selection bit. prescaler x and timer x have the prescaler x latch and the timer x latch to retain the reload value, respectively. the value of prescaler x latch is set to prescaler x when prescaler x underflows. the value of timer x latch is set to timer x when timer x underflows. when writing to prescaler x (prex) and timer x (tx) is ex- ecuted, writing to ?atch only?or ?atch and prescaler (timer)?can be selected by the setting value of the timer x write control bit. when reading from prescaler x (prex) and timer x (tx) is ex- ecuted, each count value is read out. timer x can be selected in one of 4 operating modes by setting the timer x operating mode bits of the timer x mode register. (1) timer mode prescaler x counts the count source selected by the timer x count source selection bits. each time the count clock is input, the con- tents of prescaler x is decremented by 1. when the contents of prescaler x reach ?0 16 ? an underflow occurs at the next count clock, and the prescaler x latch is reloaded into prescaler x and count continues. the division ratio of prescaler x is 1/(n+1) pro- vided that the value of prescaler x is n. the contents of timer x is decremented by 1 each time the under- flow signal of prescaler x is input. when the contents of timer x reach ?0 16 ? an underflow occurs at the next count clock, and the timer x latch is reloaded into timer x and count continues. the di- vision ratio of timer x is 1/(m+1) provided that the value of timer x is m. accordingly, the division ratio of prescaler x and timer x is 1/((n+1) ? (m+1)) provided that the value of prescaler x is n and the value of timer x is m. (2) pulse output mode in the pulse output mode, the waveform whose polarity is inverted each time timer x underflows is output from the cntr 0 pin. the output level of cntr 0 pin can be selected by the cntr 0 ac- tive edge switch bit. when the cntr 0 active edge switch bit is ?? the output of cntr 0 pin is started at ??level. when this bit is ?? the output is started at ??level. also, the inverted waveform of pulse output from cntr 0 pin can be output from tx out pin by setting ??to the p0 3 /tx out output valid bit. when using a timer in this mode, set the port p1 4 and p0 3 direc- tion registers to output mode. (3) event counter mode the timer a counts signals input from the p1 4 /cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 0 pin input signal can be selected from rising or falling by the cntr 0 active edge switch bit . 7544 group rev.1.04 2004.06.08 page 25 of 66 rej03b0012-0104z fig. 24 structure of timer x mode register fig. 25 timer count source set register 1 timer x mode register (txm : address 002b 16 , initial value: 00 16 ) timer x operating mode bits b1 b0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 0 active edge switch bit 0 : interrupt at falling edge count at rising edge (in event counter mode) 1 : interrupt at rising edge count at falling edge (in event counter mode) timer x count stop bit 0 : count start 1 : count stop p0 3 /tx out output valid bit 0 : output invalid (i/o port) 1 : output valid (inverted cntr 0 output) disable (return ??when read) b7 b0 timer count source set register 1 (tcss1 : address 002e 16 , initial value: 00 16 ) b7 b0 timer x count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) (note) 1 1 : not available note : f(x in ) can be used as timer x count source when using a ceramic resonator or on-chip oscillator. do not use it at rc oscillation. disable (return ??when read) 7544 group rev.1.04 2004.06.08 page 26 of 66 rej03b0012-0104z fig. 26 block diagram of timer 1 and timer a timer a (low-order) latch (8) timer a (low-order) (8) timer a (high-order) latch (8) timer a (high-order) (8) data bus p0 0 /cntr 1 cntr 1 active edge switch bit rising edge detected falling edge detected timer a operation mode bit timer a count stop bit prescaler 1 latch (8) prescaler 1 (8) timer 1 latch (8) timer 1 (8) data bus timer a interrupt request bit timer 1 interrupt request bit pulse width hl continuously measurement mode period measurement mode f(x in )/16 f(x in )/2 on-chip oscillator clock ring f(x in )/16 f(x in )/2 on-chip oscillator clock ring fig. 27 block diagram of timer x q q p1 4 /cntr 0 r t f(x in )/16 f(x in )/2 timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode cntr 0 interrupt request bit pulse output mode port p1 4 latch port p1 4 direction register cntr 0 active edge switch bit timer mode pulse output mode cntr 0 active edge switch bit timer x count source selection bits f(x in ) p0 3 /tx out prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) data bus ? ? ? ? writing to timer x latch p0 3 /tx out output valid port p0 3 latch port p0 3 direction register pulse output mode timer x write control bit 7544 group rev.1.04 2004.06.08 page 27 of 66 rej03b0012-0104z fig. 28 block diagram of clock synchronous serial i/o fig. 29 operation of clock synchronous serial i/o function serial i/o serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o mode selection bit of the serial i/o control register (bit 6) to ?? for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. 1/4 1/4 f/f p1 2 /s clk serial i/o status register serial i/o control register p1 3 /s rdy p1 0 /r x d p1 1 /t x d x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd w rite pulse to receive/transmit b uffer register (address 0018 16 ) overrun error (oe ) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy 7544 group rev.1.04 2004.06.08 page 28 of 66 rej03b0012-0104z fig. 30 block diagram of uart serial i/o (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to ?? eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 31 operation of uart serial i/o function x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o control register p1 2 /s clk serial i/o status register p1 0 /r x d p1 1 /t x d tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp t ransmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?,? can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ? ? serial output t x d serial input r x d receive buffer read signal 7544 group rev.1.04 2004.06.08 page 29 of 66 rej03b0012-0104z [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is ?? [serial i/o status register (siosts)] 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ??when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ??to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o status register are initialized to ??at re- set, but if the transmit enable bit of the serial i/o control register has been set to ?? the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become ?? [serial i/o control register (siocon)] 001a 16 the serial i/o control register consists of eight control bits for the serial i/o function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p1 1 /txd pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o ?serial i/o interrupt when setting the transmit enable bit to ?? the serial i/o transmit interrupt request bit is automatically set to ?? when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to ??(disabled). ? set the transmit enable bit to ?? ? set the serial i/o transmit interrupt request bit to ??after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to ??(enabled). ?i/o pin function when serial i/o is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o mode selection bit and a serial i/o synchronous clock selection bit as follows. (1) serial i/o mode selection bit ??: clock synchronous type serial i/o is selected. setup of a serial i/o synchronous clock selection bit ??: p1 2 pin turns into an output pin of a synchronous clock. ??: p1 2 pin turns into an input pin of a synchronous clock. setup of a srdy output enable bit (srdy) ??: p1 3 pin can be used as a normal i/o pin. ??: p1 3 pin turns into a srdy output pin. (2) serial i/o mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o synchronous clock selection bit ?? p1 2 pin can be used as a normal i/o pin. ?? p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin. 7544 group rev.1.04 2004.06.08 page 30 of 66 rej03b0012-0104z fig. 32 structure of serial i/o-related registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 disable (returns 1 when read) serial i/o status register serial i/o control register b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p1 3 pin operates as ordinary i/o pin 1: p1 3 pin operates as s rdy output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p1 0 to p1 3 operate as ordinary i/o pins) 1: serial i/o enabled (pins p1 0 to p1 3 operate as serial i/o pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p1 1 /t x d 1 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) disable (return 1 when read) b0 (siosts : address 0019 16 , initial value: 00 16 ) (siocon : address 001a 16 , initial value: 00 16 ) (uartcon : address 001b 16 , initial value: e0 16 ) 7544 group rev.1.04 2004.06.08 page 31 of 66 rej03b0012-0104z a/d converter the functional blocks of the a/d converter are described below. [a/d conversion register] ad the a/d conversion register is a read-only register that stores the result of a/d conversion. do not read out this register during an a/ d conversion. [a/d control register] adcon the a/d control register controls the a/d converter. bit 2 to 0 are analog input pin selection bits. bit 4 is the ad conversion comple- tion bit. the value of this bit remains at ??during a/d conversion, and changes to ??at completion of a/d conversion. a/d conversion is started by setting this bit to ?? [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref by 256, and outputs the divided voltages. [channel selector] the channel selector selects one of ports p2 5 /an 5 to p2 0 /an 0 , and inputs the voltage to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores its result into the a/d conversion register. when a/d conversion is completed, the con- trol circuit sets the ad conversion completion bit and the ad interrupt request bit to ?? because the comparator is constructed linked to a capacitor, set f(x in ) to 500 khz or more during a/d con- version. fig. 33 structure of a/d control register fig. 34 block diagram of a/d converter b7 b0 analog input pin selection bits a/d control register (adcon : address 0034 16 , initial value: 10 16 ) disable (returns ??when read) 1 : conversion completed 0 : conversion in progress ad conversion completion bit disable (returns ??when read) 111 : disable 110 : disable 101 : p2 5 /an 5 100 : p2 4 /an 4 011 : p2 3 /an 3 010 : p2 2 /an 2 001 : p2 1 /an 1 000 : p2 0 /an 0 a/d control register (address 0034 16 ) channel selector a/d control circuit resistor ladder v ref comparator a/d interrupt request b7 b0 d ata bus 3 10 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 (address 0035 16 ) v ss a/d conversion register (low-order) notes on a/d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is 500 khz or more during a/d conversion. as for ad translation accuracy, on the following operating condi- tions, accuracy may become low. (1) since the analog circuit inside a microcomputer becomes sen- sitive to noise when v ref voltage is set up lower than vcc voltage, accuracy may become low rather than the case where v ref voltage and vcc voltage are set up to the same value.. (2) when v ref voltage is lower than [ 3.0 v ], the accuracy at the low temperature may become extremely low compared with that at room temperature. when the system would be used at low temperature, the use at v ref =3.0 v or more is recom- mended. 7544 group rev.1.04 2004.06.08 page 32 of 66 rej03b0012-0104z watchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of an 8-bit watchdog timer h and an 8-bit watchdog timer l, being a 16-bit counter. standard operation of watchdog timer the watchdog timer stops when the watchdog timer control regis- ter (address 0039 16 ) is not set after reset. writing an optional value to the watchdog timer control register (address 0039 16 ) causes the watchdog timer to start to count down. when the watchdog timer h underflows, an internal reset occurs. accord- ingly, it is programmed that the watchdog timer control register (address 0039 16 ) can be set before an underflow occurs. when the watchdog timer control register (address 0039 16 ) is read, the values of the high-order 6-bit of the watchdog timer h, stp instruction disable bit and watchdog timer h count source se- lection bit are read. initial value of watchdog timer by a reset or writing to the watchdog timer control register (ad- dress 0039 16 ), the watchdog timer h is set to ?f 16 ?and the watchdog timer l is set to ?f 16 ? operation of watchdog timer h count source selection bit a watchdog timer h count source can be selected by bit 7 of the watchdog timer control register (address 0039 16 ). when this bit is ?? the count source becomes a watchdog timer l underflow sig- nal. the detection time is 131.072 ms at f(x in )=8 mhz. when this bit is ?? the count source becomes f(x in )/16. in this case, the detection time is 512 s at f(x in )=8 mhz. this bit is cleared to ??after reset. operation of stp instruction disable bit when the watchdog timer is in operation, the stp instruction can be disabled by bit 6 of the watchdog timer control register (ad- dress 0039 16 ). when this bit is ?? the stp instruction is enabled. when this bit is ?? the stp instruction is disabled, and an inter- nal reset occurs if the stp instruction is executed. once this bit is set to ?? it cannot be changed to ??by program. this bit is cleared to ??after reset. fig. 35 block diagram of watchdog timer fig. 36 structure of watchdog timer control register x in data bus ? ? 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) write "ff 16 " to th e watchdog timer control register internal reset reset watchdog timer l (8) stp instruction write ?f 16 ?to the watchdog timer control register watchdog timer control register (wdtcon: address 0039 16 , initial value: 3f 16 ) watchdog timer h (read only for high-order 6-bit) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 b7 b0 7544 group rev.1.04 2004.06.08 page 33 of 66 rej03b0012-0104z reset circuit the microcomputer is put into a reset status by holding the re- set pin at the ??level for 2 s or more when the power source voltage is 4.5 to 5.5 v and x in is in stable oscillation. ______ after that, this reset status is released by returning the reset pin to the ??level. the program starts from the address having the contents of address fffd 16 as high-order address and the con- tents of address fffc 16 as low-order address. in the case of f( ) 8 mhz, the reset input voltage must be 0.9 v or less when the power source voltage passes 4.5 v. fig. 37 example of reset circuit fig. 38 timing diagram at reset (note) 0.2 v cc 0 v 0 v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage vcc 4.5v data address 8-13 clock cycles reset address from the vector table 1 : an on-chip oscillator applies about ring? mhz, ?50 khz frequency clock at average of vcc = 5 v. 2 : the mark ??means that the address is changeable depending on the previous state. 3 : these are all internal signals except reset. notes ?? fffc fffd ad h ,ad l ??? ?? ad l ad h ??? clock from on-chip oscillator ring reset reset out sync 7544 group rev.1.04 2004.06.08 page 34 of 66 rej03b0012-0104z fig. 39 internal status of microcomputer at reset x : undefined the content of other registers is undefined when the microcomputer is reset. the initial values must be surely set bifore you use it. register contents address ( 1) ( 2) ( 3) ( 4) ( 5) ( 6) ( 7) ( 8) ( 9) ( 10) ( 11) ( 12) ( 13) ( 14) ( 15) ( 16) ( 17) ( 18) ( 19) ( 20) ( 21) ( 22) ( 23) ( 24) ( 25) ( 26) ( 27) ( 28) ( 29) ( 30) port p0 direction register port p1 direction register port p2 direction register port p3 direction register pull-up control register port p1p3 control register serial i/o status register serial i/o control register uart control registe timer a mode register timer a (low-order) timer a (high-order) prescaler 1 timer 1 timer x mode register prescaler x timer x timer count source set register 1 timer count source set register 2 a/d control register misrg watchdog timer control register interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register program counter 0001 16 0003 16 0005 16 0007 16 0016 16 0017 16 0019 16 001a 16 001b 16 001d 16 001e 16 001f 16 0028 16 0029 16 002b 16 002c 16 002d 16 002e 16 002f 16 0034 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pc h ) (pc l ) 00 16 00 16 xx 00 00 x0 xx 00 00 00 0x 00 00 x0 00 16 10 0000 00 11 0000 10 00 16 ff 16 ff 16 ff 16 00 0001 00 00 16 ff 16 ff 16 00 16 00 0000 01 00 16 00 1111 11 00 16 00 16 00 16 10 0000 00 00 16 00 16 00 16 00 16 xx x 1xx xx contents of address fffd 16 contents of address fffc 16 7544 group rev.1.04 2004.06.08 page 35 of 66 rej03b0012-0104z fig. 41 external circuit of ceramic resonator and quartz-crystal oscillator fig. 43 external clock input circuit fig. 40 processing of x in and x out pins at on-chip oscillator opera- tion clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out , and an rc oscillation circuit can be formed by connecting a resistor and a capacitor. use the circuit constants in accordance with the resonator manufacturer's recommended values. (1) on-chip oscillator operation when the mcu operates by the on-chip oscillator for the main clock, connect x in pin to v cc and leave x out pin open. the clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (2) ceramic resonator and quartz-crystal oscillator when the ceramic resonator and quartz-crystal oscillator is used for the main clock, connect the ceramic/quartz-crystal oscillator and the external circuit to pins x in and x out at the shortest dis- tance. a feedback resistor is built in between pins x in and x out . (3) rc oscillation when the rc oscillation is used for the main clock, connect the x in pin and x out pin to the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. (4) external clock when the external signal clock is used for the main clock, connect the x in pin to the clock source and leave x out pin open. externally connect a damping resistor rd depending on the oscil- lation frequency. (a feedback resistor is built-in.) use the resonator manufacturer s recom- mended value because constants such as ca- pacitance depend on the resonator. note: connect the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is af- fected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. note: the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that variable fre- quencies and obtain the sufficient margin. note: x in x out m37544 open x in c ou t c in x out m37544 rd x in x out c r m37544 x in x out e xternal oscillation c ircuit v cc v ss open m37544 fig. 42 external circuit of rc oscillation 7544 group rev.1.04 2004.06.08 page 36 of 66 rej03b0012-0104z fig. 44 structure of cpu mode register (1) oscillation control ?stop mode when the stp instruction is executed, the internal clock stops at an ??level and the x in oscillator stops. at this time, timer 1 is set to ?1 16 ?and prescaler 1 is set to ?f 16 ?when the oscillation sta- bilization time set bit after release of the stp instruction is ?? on the other hand, timer 1 and prescaler 1 are not set when the above bit is ?? accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. single selected by the timer 1 count source selection bit is connected to the input of prescaler 1. when an external interrupt is accepted, oscillation is restarted but the internal clock remains at ??until timer 1 underflows. as soon as timer 1 underflows, the internal clock is supplied. this is because when a ceramic/quartz-crystal oscillator is used, some time is required until a start of oscillation. in case oscillation is restarted by reset, no wait time is generated. so ap- ______ ply an ??level to the reset pin while oscillation becomes stable. also, the stp instruction cannot be used while cpu is operating by an on-chip oscillator. ?wait mode if the wit instruction is executed, the internal clock stops at an ??level, but the oscillator does not stop. the internal clock re- starts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to ??before the stp or wit instruction is executed. notes on clock generating circuit for use with the oscillation stabilization set bit after release of the stp instruction set to ?? set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used. ?switch of ceramic/quartz-crystal and rc oscillations after releasing reset the operation starts by starting an on-chip os- cillator. then, a ceramic/quartz-crystal oscillation or an rc oscillation is selected by setting bit 5 of the cpu mode register. ?double-speed mode when a ceramic/quartz-crystal oscillation is selected, a double- speed mode can be used. do not use it when an rc oscillation is selected. ?cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. after rewriting it is disable to write any data to the bit. (the emulator mcu ?37544rss?is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. ?clock division ratio, x in oscillation control, on-chip oscillator con- trol the state transition shown in fig. 48 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 48. processor mode bits (note 1) b1 b0 0 0 single-chip mode 0 1 1 0 1 1 not available b7 b0 2: these bits are used only when a ceramic /quartz-crystal oscillation is selected. note 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu ?37544rss?) do not use these when an rc oscillation is selected. oscillation mode selection bit (note 1) 0 : ceramic/quartz-crystal oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( ) = f(x in )/2 (high-speed mode) 0 1 : f( ) = f(x in )/8 (middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f( ) = f(x in ) (double-speed mode)(note 2) on-chip oscillator oscillation control bit 0 : on-chip oscillator oscillation enabled 1 : on-chip oscillator oscillation stop x in oscillation control bit 0 : ceramic/quartz-crystal or rc oscillation enabled 1 : ceramic/quartz-crystal or rc oscillation stop 7544 group rev.1.04 2004.06.08 page 37 of 66 rej03b0012-0104z oscillation stop detection circuit the oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or an oscillation circuit stops by discon- nection. when internal reset occurs, reset because of oscillation stop can be detected by setting ??to the oscillation stop detection status bit. also, when using the oscillation stop detection circuit, an on-chip oscillator is required. figure 48 shows the state transition. the oscillation stop detection status bit retains ?? not initialized, when the oscillation stop reset occurs. the oscillation stop detec- tion status bit is initialized to ??when the external reset occurs. accordingly, reset by oscillation stop can be confirmed by using this bit. notes on oscillation stop detection circuit ? oscillation stop detection status bit is initialized by the following operation. (1) external reset (2) write ??data to the ceramic or rc oscillation stop detection function active bit. ? the oscillation stop detection circuit is not included in the emu- lator mcu ?37544rss? fig. 45 structure of misrg misrg(address 0038 16 , initial value: 00 1 6 ) b7 b0 oscillation stabilization time set bit after release of the stp instruction 0: set ?1 16 ?in timer1, and ?f 16 in prescaler 1 automatically 1: not set automatically ceramic/quartz-crystal or rc oscillation stop detection function active bit 0: detection function inactive 1: detection function active reserved bits (return ??when read) (do not write ??to these bits) disable (return ??when read) oscillation stop detection status bit 0: oscillation stop not detected 1: oscillation stop detected 7544 group rev.1.04 2004.06.08 page 38 of 66 rej03b0012-0104z fig. 46 block diagram of internal clock generating circuit (for ceramic/quartz-crystal resonator) fig. 47 block diagram of internal clock generating circuit (for rc oscillation) s r q s r q 1/2 r s q rf 1/4 1/2 wit instruction stp instruction timing (internal clock) stp instruction interrupt request reset i nterrupt disable flag l high-speed mode middle-speed mode clock division ratio selection bit double-speed mode on-chip oscillator mode on-chip oscillator ring x out x in 1/8 clock division ratio selection bit middle-, high-, low-speed mode on-chip oscillator mode rese t prescaler 1 timer 1 s r q s r q 1/2 r s q 1/4 1/2 wit instruction stp instruction timing (internal clock) stp instruction interrupt request reset interrupt disable flag l high-speed mode middle-speed mode clock division ratio selection bit double-speed mode on-chip oscillator mode on-chip oscillator ring x out x in delay 1/8 clock division ratio selection bit middle-, high-, low-speed mode on-chip oscillator mode rese t prescaler 1 timer 1 7544 group rev.1.04 2004.06.08 page 39 of 66 rej03b0012-0104z fig. 48 state transition stop mode wait mode wit instruction oscillation stop detection circuit valid cpum 4 1 2 misrg 1 1 2 interrupt interrupt stp instruction wit instruction interrupt misrg 1 0 2 cpum 3 1 2 cpum 3 0 2 cpum 76 10 2 cpum 76 00 2 01 2 11 2 (note 2) cpum 4 0 2 misrg 1 1 2 misrg 1 0 2 reset released state 1 operation clock source: f(x in ) (note 1) f(x in ) oscillation enabled on-chip oscillator stop state 2 operation clock source: f(x in ) (note 1) f(x in ) oscillation enabled on-chip oscillator enabled state 3 operation clock source: on-chip oscillator (note 3) f(x in ) oscillation enabled on-chip oscillator enabled state 4 operation clock source: on-chip oscillator (note 3) f(x in ) oscillation stop on-chip oscillator enabled notes on switch of clock (1) in operation clock source = f(x in ), the following can be selected for the cpu clock division ratio. f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) f(x in ) (double-speed mode, only at a ceramic/quartz-crysta l oscillation) (2) execute the state transition state 3 to state 2 or state 3?to state 2?after stabilizing x in oscillation. (3) in operation clock source = on-chip oscillator, the middle- speed mode is selected for the cpu clock division ratio. (4) when the state transition state 2 state 3 state 4 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. ?cpum76 10 2 (state 2 state 3) ?nop instruction ?cpum4 1 2 (state 3 state 4) double-speed mode at on-chip oscillator: nop 3 high-speed mode at on-chip oscillator: nop 1 middle-speed mode at on-chip oscillator: nop 0 reset state cpum 76 10 2 cpum 76 00 2 01 2 11 2 (note 2) state 2 operation clock source: f(x in ) (note 1) f(x in ) oscillation enabled on-chip oscillator enabled state 3? operation clock source: on-chip oscillator (note 3) f(x in ) oscillation enabled on-chip oscillator enabled 7544 group rev.1.04 2004.06.08 page 40 of 66 rej03b0012-0104z notes on programming processor status register the contents of the processor status register (ps) after reset are undefined except for the interrupt disable flag i which is ?? after reset, initialize flags which affect program execution. in particular, it is essential to initialize the t flag and the d flag because of their effect on calculations. interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. for executing the instruction for the changed contents, execute one instruction before executing the bbc or bbs instruction. decimal calculations ?for calculations in decimal notation, set the decimal mode flag d to ?? then execute the adc instruction or sbc instruction. in this case, execute sec instruction, clc instruction or cld in- struction after executing one instruction before the adc instruction or sbc instruction. ?in the decimal mode, the values of the n (negative), v (overflow) and z (zero) flags are invalid. ports ?the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory opera- tion instruction when the t flag is ?? addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb and read/modify/write instructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta in- struction, etc. a/d conversion do not execute the stp instruction during a/d conversion. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles men- tioned in the machine-language instruction table. the frequency of the internal clock is the same as that of the x in in double-speed mode, twice the x in cycle in high-speed mode and 8 times the x in cycle in middle-speed mode. cpu mode register the oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. however, after rewriting it is disable to write any value to the bit. (emulator mcu is ex- cluded.) when a ceramic / quartz-crystal oscillation is selected, a double- speed mode of the clock division ratio selection bits can be used. do not use it when an rc oscillation is selected. state transition do not stop the clock selected as the operation clock because of setting of cm3, 4. notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 f to 0.1 f is recommended. one time prom version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin with 1 to 10 k ? resistance. the mask rom version track of cnvss pin has no operational in- terference even if it is connected via a resistor. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form * 2.mark specification form * for the mask rom confirmation and the mark specifications, refer to the "renesas technology corp." homepage (http://www.renesas.com/en/rom). 7544 group rev.1.04 2004.06.08 page 41 of 66 rej03b0012-0104z notes on use countermeasures against noise 1. shortest wiring length (1) package select the smallest possible package to make the total wiring length short. 7544 group rev.1.04 2004.06.08 page 42 of 66 rej03b0012-0104z fig. 54 bypass capacitor across the v ss line and the v cc line 2. connection of bypass capacitor across v ss line and v cc line connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: ?connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ?connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ?use lines with a larger diameter than other signal lines for v ss line and v cc line. ?connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. 3. wiring to analog input pins ?connect an approximately 100 ? to 1 k ? resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. ?connect an approximately 1000 pf capacitor across the vss pin and the analog input pin. besides, connect the capacitor to the vss pin as close as possible. also, connect the capacitor across the analog input pin and the vss pin at equal length. 7544 group rev.1.04 2004.06.08 page 43 of 66 rej03b0012-0104z 4. oscillator concerns so that the product obtains the stabilized operation clock on the user system and its condition, contact the resonator manufacturer and select the resonator and oscillation circuit constants. be careful especially when range of voltage and temperature is wide. take care to prevent an oscillator that generates clocks for a mi- crocomputer operation from being affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. 7544 group rev.1.04 2004.06.08 page 44 of 66 rej03b0012-0104z 5. setup for i/o ports setup i/o ports using hardware and software as follows: 7544 group rev.1.04 2004.06.08 page 45 of 66 rej03b0012-0104z prom mode m37544g2sp/gp (referred to as ?he mcu? has a prom mode as well as the normal operation mode. prom mode enables an external device (referred to as ?rogrammer? to read and pro- gram the built-in eprom via a minimum number of serial i/o pins by sending commands to control the mcu. to enable prom mode, use the pin connection shown in figure 60 to 61 and apply power (v cc ). then execute the new otp en- try operation, called ?ad dog entry? there are three operation modes in prom mode : read, program and program-verify. three commands are defined to enable each mode respectively. the format of the serial i/o is : clock synchronous and lsb-data- first. p1 2 /s clk m37544g2sp 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p1 3 /s rdy p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref cnv ss v cc x in x out v ss reset p1 1 /t x d p1 0 /r x d p0 7 (led 7 ) p0 6 (led 6 ) p0 5 (led 5 ) p0 4 (led 4 ) p0 3 (led 3 )/tx out p0 2 (led 2 ) p0 1 (led 1 ) p0 0 (led 0 )/cntr 1 p3 4 (led 12 )/int 1 p3 3 (led 11 ) p3 2 (led 10 ) p3 1 (led 9 ) p3 0 (led 8 ) p3 7 (led 13 )/int 0 esclk resetb vpp vcc xin xout vss esda espgmb fig. 60 ?ad dog entry?pin diagram (32p4b) 7544 group rev.1.04 2004.06.08 page 46 of 66 rej03b0012-0104z fig. 61 ?ad dog entry?pin diagram (32p6u-a) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 8 7 6 5 3 4 v cc cnv ss p2 2 /an 2 p0 5 (led 5 ) p0 2 (led 2 ) p0 4 (led 4 ) p0 3 (le d3 )/tx out p0 6 (led 6 ) p0 1 (led 1 ) p0 0 (led 0 )/cntr 1 p3 7 (led 13 )/int 0 m37544g2gp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref reset 1 2 p2 0 / an 0 p2 1 / an 1 p1 4 /cntr 0 p1 3 /s rdy p1 2 /s clk p1 1 /t x d p1 0 /r x d p0 7 (led 7 ) x out x in v ss p3 0 (led 8 ) p3 1 (led 9 ) p3 2 (led 10 ) p3 3 (led 11 ) p3 4 (led 12 )/int 1 24 23 22 21 20 19 18 17 esclk xin xout vss esda espgmb vpp resetb vcc 7544 group rev.1.04 2004.06.08 page 47 of 66 rej03b0012-0104z programming with prom programmer screening (caution) (150 ? for 40 hours) verification with prom programmer functional check in target device the screening temperature is far high er than the storage temperature. nev er expose to 150 ? exceeding 100 hours . c aution: fig. 62 programming and testing of one time prom precaution for handling one-time-programmable devices our company ships one-time-programmable version mcus (one- time prom mcu) without being screened by the prom writing test. to ensure the reliability of the mcu, we recommend that the user performs the program and test procedure shown in figure 62 before using the mcu. 7544 group rev.1.04 2004.06.08 page 48 of 66 rej03b0012-0104z rom code access protection we would like to support a simple rom code protection function that prevents a party other than the rom-code owner to read and reprogram the builit-in prom code of the mcu. the mcu has 7 bytes of dedicated rom spaces in address 0xffd4 to 0xffda, as an id-code (referred to as ?he id-code? enabling a programmer to verify with the input id-code and validate further operations. expected programmer id-code verification function first, programmer must check the id-code of the mcu. if the id-code is still in blank, programmer enables all operations, read, program, and program-verify. when programmer programs the mcu, programmer also programs the given id-code as well as the actual firmware. if the id-code is not blank, programmer verifies it with the input id-code. when the id-codes don't match, programmer will reject all further operations. if they match, programmer perform operations according to the given command. id1 id2 id3 id4 id5 id6 id7 address ffd4 16 ffd5 16 ffd6 16 ffd7 16 ffd8 16 ffd9 16 ffda 16 fig. 63 rom-code protection id location 7544 group rev.1.04 2004.06.08 page 49 of 66 rej03b0012-0104z electrical characteristics 1.7544group applied to: m37544m2-xxxsp/gp/hp, m37544g2sp/gp/hp(note) note: m37544g2hp: only es version (mp: no plan) absolute maximum ratings table 9 absolute maximum ratings ?.3 to 6.5 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to 7.0 ?.3 to v cc + 0.3 200 ?0 to 85 ?0 to 125 power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 ,p3 7 , v ref input voltage ______ reset, x in input voltage cnv ss ( note ) output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 ,p3 7 , x out power dissipation operating temperature storage temperature v v v v v mw ? ? v cc v i v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25? notes : it is a rating only for the one time prom version. connect to v ss for the mask rom version. 7544 group rev.1.04 2004.06.08 page 50 of 66 rej03b0012-0104z power source voltage (ceramic) power source voltage (rc) power source voltage analog reference voltage ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p3 4 , p3 7 ??input voltage ______ reset, x in ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p3 4 , p3 7 ??input voltage ______ reset, cnv ss ??input voltage x in ??total peak output current ( note ) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ??total peak output current ( note ) p1 0 ?1 4 , p2 0 ?2 5 ??total peak output current ( note ) p0 0 ?0 7 , p3 0 ?3 4 , p3 7 ??total average output current ( note ) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 p3 4 , p3 7 ??total average output current ( note ) p1 0 ?1 4 , p2 0 ?2 5 ??total average output current ( note ) p0 0 ?0 7 , p3 0 ?3 4 , p3 7 recommended operating conditions table 10 recommended operating conditions (1) (v cc = 4.0 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) max. 5.5 5.5 5.5 v cc v cc v cc v cc 0.3v cc 0.8 0.2v cc 0.16v cc ?0 80 60 ?0 40 30 min. 4.0 4.5 4.0 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 symbol parameter unit f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 8 mhz (double-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) typ. 5.0 5.0 5.0 0 limits v cc v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) v v v v v v v v v v v v ma ma ma ma ma ma note : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 7544 group rev.1.04 2004.06.08 page 51 of 66 rej03b0012-0104z recommended operating conditions (continued) table 11 recommended operating conditions (2) (v cc = 4.0 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) ??peak output current ( note 1 ) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ??peak output current ( note 1 ) p1 0 ?1 4 , p2 0 ?2 5 ??peak output current ( note 1 ) p0 0 ?0 7 , p3 0 ?3 4 , p3 7 ??average output current ( note 2 ) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ??average output current ( note 2 ) p1 0 ?1 4 , p2 0 ?2 5 ??average output current ( note 2 ) p0 0 ?0 7 , p3 0 ?3 4 , p3 7 internal clock oscillation frequency ( note 3 ) at ceramic oscillation or external clock input internal clock oscillation frequency ( note 3 ) at ceramic oscillation or external clock input internal clock oscillation frequency ( note 3 ) at rc oscillation symbol parameter limits max. typ. min. ?0 10 30 ? 5 15 8 8 4 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) ma ma ma ma ma ma mhz mhz mhz unit v cc = 4.5 to 5.5 v double-speed mode v cc = 4.0 to 5.5 v high-, middle-speed mode v cc = 4.0 to 5.5 v high-, middle-speed mode 7544 group rev.1.04 2004.06.08 page 52 of 66 rej03b0012-0104z electrical characteristics table 12 electrical characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = ? ma v cc = 4.0 to 5.5 v i oh = ?.0 ma v cc = 4.0 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 4.0 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 4.0 to 5.5 v v i = v cc (pin floating. pull up transistors ?ff? v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors ?ff? v i = v ss v i = v ss v i = v ss (pull up transistors ?n? when clock stopped v cc = 5.0 v, ta = 25 ? v cc = 5.0 v, ta = 25 ? test conditions v cc ?.5 v cc ?.0 2.0 1000 62.5 ??output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ( note 1 ) ??output voltage p1 0 ?1 4 , p2 0 ?2 5 ??output voltage p0 0 ?0 7 , p3 0 ?3 4 , p3 7 hysteresis cntr 0 , cntr 1 , int 0 , int 1 ( note 2 ) p0 0 ?0 7 ( note 3 ) hysteresis r x d, s clk ( note 2 ) hysteresis ______ reset ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ??input current ______ reset ??input current x in ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 5 , p3 0 ?3 4 , p3 7 ??input current ______ reset, cnv ss ??input current x in ??input current p0 0 ?0 7 , p3 0 ?3 4 , p3 7 ram hold voltage on-chip oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 ?.0 ?.0 ?.5 5.5 3000 187.5 v v v v v v v v v v v ? ? ? ? ? ? ma v khz khz v oh v ol v ol v t+ ? t v t+ ? t v t+ ? t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.9 4.0 ?.0 ?.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? 2: r x d, s clk , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to ??(cmos level). 3: it is available only when operating key-on wake up. 7544 group rev.1.04 2004.06.08 page 53 of 66 rej03b0012-0104z electrical characteristics (continued) table 13 electrical characteristics (2) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit test conditions power source current 8.0 10.0 5.0 900 3.2 450 1.0 10.0 ma ma ma ? ma ? ma ? ? i cc 3.3 4.8 1.8 250 1.3 140 0.45 0.1 high-speed mode, f(x in ) = 8 mhz output transistors ?ff double-speed mode, f(x in ) = 8 mhz output transistors ?ff middle-speed mode, f(x in ) = 8 mhz output transistors ?ff on-chip oscillator operation mode, v cc = 5 v output transistors ?ff f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors ?ff on-chip oscillator operation mode(in wit state), v cc = 5v functions except timer 1 disabled, output transistors ?ff increment when a/d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors ?ff ta = 25 ? ta = 85 ? 7544 group rev.1.04 2004.06.08 page 54 of 66 rej03b0012-0104z a/d converter characteristics table 14 a/d converter characteristics (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) resolution absolute accuracy (quantification error excluded) conversion time ladder resistor reference power source input current a/d port input current min. typ. max. symbol parameter limits unit test conditions ta = ?0 to 85 ?, vcc = v ref v ref = 5.0 v v ref = 3.0 v bits lsb tc(x in ) k ? ? ? 8 ? 109 200 120 5.0 abs t conv r ladder i vref i i(ad) 37 135 80 50 30 timing requirements table 15 timing requirements (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input ??pulse width cntr 0 , int 0 , int 1 , input ??pulse width cntr 1 input cycle time cntr 1 input ??pulse width cntr 1 input ??pulse width serial i/o clock input cycle time (note) serial i/o clock input ??pulse width (note) serial i/o clock input ??pulse width (note) serial i/o input set up time serial i/o input hold time 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 ? ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o control register (address 001a 16 ) is set to ??(clock synchronous serial i/o is selected). when bit 6 of the serial i/o control register is ??(clock asynchronous serial i/o is selected), the rating values are divided by 4. ______ t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (rxd? clk ) t h (s clk ?xd) note: as for ad translation accuracy, on the following operating conditions, accuracy may become low. (1) since the analog circuit inside a microcomputer becomes sensitive to noise when v ref voltage is set up lower than vcc voltage, accuracy may become low rather than the case where v ref voltage and vcc voltage are set up to the same value.. (2) when v ref voltage is less than [ 3.0v ], the accuracy at the time of low temperature may become extremely low compared with the time of room temperature. the use beyond v ref =3.0v is recommended in the system the use by the side of low temperature is assumed to be. 7544 group rev.1.04 2004.06.08 page 55 of 66 rej03b0012-0104z switching characteristics table 16 switching characteristics (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) t c (s clk )/2?0 t c (s clk )/2?0 ?0 min. typ. max. symbol parameter limits unit t wh (s clk ) t wl (s clk ) t d (s clk ?xd) t v (s clk ?xd) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) serial i/o clock output ??pulse width serial i/o clock output ??pulse width serial i/o output delay time serial i/o output valid time serial i/o clock output rising time serial i/o clock output falling time cmos output rising time ( note ) cmos output falling time ( note ) note : pin x out is excluded. 10 10 140 30 30 30 30 ns ns ns ns ns ns ns ns fig. 64 switching characteristics measurement circuit diagram / / / measured output pin cmos output 100 pf 7544 group rev.1.04 2004.06.08 page 56 of 66 rej03b0012-0104z 0.2v cc t d (s clk -txd) t f 0.2v cc 0.8v cc 0.8v cc t r t su (rxd-s clk )t h (s clk -rxd) t v (s clk -txd ) t c (s clk ) t wl (s clk ) t wh (s clk ) r x d (at receive) s clk 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 fig. 65 timing chart 7544 group rev.1.04 2004.06.08 page 57 of 66 rej03b0012-0104z package outline lqfp32-p-0707-0.80 weight(g) jedec code eiaj package code lead material cu alloy 3 2p6u-a plastic 32pin 7 ? 7mm body lqf p 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 i 2 1.0 m d m e 10 0 0.1 1.0 0.7 0.2 0.5 0.3 0.8 6.9 7.0 7.1 6.9 7.0 7.1 8.8 9.0 9.2 8.8 9.0 9.2 0.175 0.125 0.105 0.45 0.37 0.32 1.4 0 1.7 e lp 0.45 0.6 0.5 7.4 7.4 0.25 0.75 x a3 recommended mount pad detail f a e h e h d d 1 8 24 17 25 32 16 9 m d b 2 m e e f e y b x m a 1 a 2 l l 1 lp a3 c i 2 recommended sdip32-p-400-1.78 weight(g) 2.2 jedec code eiaj package code lead material alloy 42/cu alloy 32p4b plastic 32pin 400mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 1.778 10.16 3.0 0 ?5 5.08 e e 1 32 17 16 1 e c e 1 a 2 a 1 b 2 b b 1 e la seating plane d recommended 7544 group rev.1.04 2004.06.08 page 58 of 66 rej03b0012-0104z wqfn36-p-0606-0.50 jedec code eiaj package code lead material 3 6pjw-a plastic 36pin 6x6mm body wqf n 0.2 symbol min nom max a b c d e y b 2 dimension in millimeters i 2 m d m e 4.8 0.7 5.9 5.9 0.6 0.7 6.1 6.1 0.5 0.3 0.25 0.05 0.05 0.15 0.2 6.0 6.0 0.5 0.8 e lp 4.8 x recommended mount pad cu alloy weight(g) 0.83 x y lp a e d c 4.26 (typ.) e b 28 18 36 10 18 10 1 9 19 9 27 1 28 36 m 4.26 (typ.) b 2 m e e 27 19 i 2 m d 7544 group rev.1.04 2004.06.08 page 59 of 66 rej03b0012-0104z appendix notes on programming 1. processor status register (1) initializing of processor status register flags which affect program execution must be initialized after a re- set. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. 7544 group rev.1.04 2004.06.08 page 60 of 66 rej03b0012-0104z 6. read-modify-write instruction do not execute a read-modify-write instruction to the read invalid address (sfr). the read-modify-write instruction operates in the following se- quence: read one-byte of data from memory, modify the data, write the data back to original memory. the following instructions are classified as the read-modify-write instructions in the 740 family. (1) bit management instructions: clb, seb (2) shift and rotate instructions: asl, lsr, rol, ror, rrf (3) add and subtract instructions: dec, inc (4) logical operation instructions (1 s complement): com add and subtract/logical operation instructions (adc, sbc, and, eor, and ora) when t flag = ?? operate in the way as the read- modify-write instruction. do not execute the read invalid sfr. 7544 group rev.1.04 2004.06.08 page 61 of 66 rej03b0012-0104z termination of unused pins 1. terminate unused pins perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) i/o ports set the i/o ports for the input mode and connect each pin to v cc or v ss through each resistor of 1 k ? to 10 k ? . the port which can select a built-in pull-up resistor can also use the built-in pull-up re- sistor. when using the i/o ports as the output mode, open them at ??or ?? ?when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the poten- tial at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the sys- tem, thoroughly perform system evaluation on the user side. ?since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. termination remarks (1) i/o ports setting as input mode [1] do not open in the input mode. 7544 group rev.1.04 2004.06.08 page 62 of 66 rej03b0012-0104z notes on timers 1. when n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). 2. when a count source of timer x is switched, stop a count of the timer. notes on timer 1 1. timer 1 count source the ?n-chip oscillator output?of timer 1 count source selection bits (bits 1 and 0 of timer count source set register 2 (address 2f 16 )) can be selected while the on-chip oscillator oscillation con- trol bit (bit 3 of cpu mode register (address 3b 16 )) is ??(on-chip oscillator oscillation enabled). notes on timer a 1. cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit (bit 6 of timer a mode register (address 1d 16 )). when this bit is ?? the cntr 1 interrupt request bit goes to ??at the falling edge of the cntr 1 pin input signal. when this bit is ?? the cntr 1 interrupt request bit goes to ??at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. 2. period measurement mode, event counter mode and pulse width hl continuously measurement mode set the direction register of port p0 0 , which is also used as cntr 1 pin, to input. set the key-on wakeup function of p0 0 , which is also used as cntr 1 pin, to be disabled by setting the p0 0 key-on wakeup se- lection bit (bit 7 of interrupt edge selection register (address 3a 16 )) to ?? 3. timer a count source the ?n-chip oscillator output?of timer a count source selection bits (bits 3 and 2 of timer count source set register 2 (address 2f 16 )) can be selected while the on-chip oscillator oscillation con- trol bit (bit 3 of cpu mode register (address 3b 16 )) is ??(on-chip oscillator oscillation enabled). notes on timer x 1. cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit (bit 2 of timer x mode register (address 2b 16 )). when this bit is ?? the cntr 0 interrupt request bit goes to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit goes to ??at the rising edge of cntr 0 pin input signal. 2. timer x count source selection the f(x in ) (frequency not divided) can be selected by the timer x count source selection bits (bits 1 and 0 of timer count source set register 1 (address 2e 16 )) only when the ceramic oscillation or the on-chip oscillator is selected. do not select it for the timer x count source at the rc oscillation. 3. pulse output mode set the direction register of port p1 4 , which is also used as cntr 0 pin, to output. when the tx out pin is used, set the direction register of port p0 3 , which is also used as tx out pin, to output. 4. pulse width measurement mode set the direction register of port p1 4 , which is also used as cntr 0 pin, to input. 7544 group rev.1.04 2004.06.08 page 63 of 66 rej03b0012-0104z 3. notes common to clock synchronous serial i/o and uart (1) set the serial i/o control register again after the transmission and the reception circuits are reset by clearing both the trans- mit enable bit and the receive enable bit to ?. fig. 7 sequence of setting serial i/o control register again clear both the transmit enable bit (te) and the receive enable bit (re) to ? set the bits 0 to 3 and bit 6 of the serial i/o control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ? notes on serial i/o 1. clock synchronous serial i/o (1) when the transmit operation is stopped, clear the serial i/o en- able bit (bit 7) and the transmit enable bit (bit 4 of serial i/o control register (address 1a 16 )) to ??(serial i/o and transmit disabled). 7544 group rev.1.04 2004.06.08 page 64 of 66 rej03b0012-0104z 4. i/o pin function when serial i/o is enabled. the pin functions of p1 2 /s clk and p1 3 /s rdy are switched to as follows according to the setting values of a serial i/o mode selec- tion bit (bit 6 of serial i/o control register (address 1a 16 )) and a serial i/o synchronous clock selection bit (bit 1 of serial i/o control register). (1) serial i/o mode selection bit ??: clock synchronous type serial i/o is selected. ?setup of a serial i/o synchronous clock selection bit ??: p1 2 pin turns into an output pin of a synchronous clock. ??: p1 2 pin turns into an input pin of a synchronous clock. ?setup of a s rdy output enable bit (srdy) ??: p1 3 pin can be used as a normal i/o pin. ??: p1 3 pin turns into a s rdy output pin. (2) serial i/o mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. ?setup of a serial i/o synchronous clock selection bit ?? p1 2 pin can be used as a normal i/o pin. ?? p1 2 pin turns into an input pin of an external clock. ?when clock asynchronous (uart) type serial i/o is selected, it functions p1 3 pin. it can be used as a normal i/o pin. notes on a/d conversion 1. analog input pin in order to execute the a/d conversion correctly, to complete the charge to an internal capacitor within the specified time is re- quired. the maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; about 35 k ? (at f(x in ) = 8 mhz) when the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01 f to 1 f between an analog input pin and v ss . further, be sure to verify the operation of application products on the user side. 7544 group rev.1.04 2004.06.08 page 65 of 66 rej03b0012-0104z notes on clock generating circuit 1. switch of ceramic/quartz-crystal oscillation and rc oscillation after releasing reset, the oscillation mode selection bit (bit 5 of cpu mode register (address 3b 16 )) is ??(ceramic/quartz-crystal oscillation selected). when the rc oscillation is used, after releas- ing reset, set this bit to ?? 2. double-speed mode the double-speed mode can be used only when a ceramic oscilla- tion is selected. do not use it when an rc oscillation is selected. 3. cpu mode register oscillation mode selection bit (bit 5), processor mode bits (bits 1 and 0) of cpu mode register (address 3b 16 ) are used to select os- cillation mode and to control operation modes of the microcomputer. in order to prevent the dead-lock by erroneously writing (ex. program run-away), these bits can be rewritten only once after releasing reset. after rewriting, it is disabled to write any data to the bit. (the emulator mcu ?37542rss?is excluded.) also, when the read-modify-write instructions (seb, clb, etc.) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. 4. clock division ratio, x in oscillation control, on-chip oscillator control the state transition shown in fig. 81 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 81. 5. on-chip oscillator operation when the mcu operates by the on-chip oscillator for the main clock, connect x in pin to v cc through a 1 k ? to 10 k ? resistor and leave x out pin open. the clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. be careful that this margin of frequencies when designing applica- tion products. 6. ceramic resonator when the ceramic resonator/quartz-crystal oscillation is used for the main clock, connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built-in. 7. rc oscillation when the rc oscillation is used for the main clock, connect the x in pin and x out pin to the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. 8. external clock when the external signal clock is used for the main clock, connect the x in pin to the clock source and leave x out pin open. select ??(ceramic oscillation) to oscillation mode selection bit. notes on oscillation control 1. oscillation stop detection circuit (1) when the stop mode is used, set the oscillation stop detection function to ?nvalid? (2) when the ceramic or rc oscillation is stopped (bit 4 of cpu mode register (address 3b 16 )), set the oscillation stop detec- tion function to ?nvalid? (3) the oscillation stop detection circuit is not included in the emu- lator mcu ?37542rss? 2. stop mode (1) when the stop mode is used, set the oscillation stop detection function to ?nvalid? (2) when the stop mode is used, set ??( stp instruction enabled) to the stp instruction disable bit of the watchdog timer control register (bit 6 of watchdog timer control register (address 39 16 )). (3) the oscillation stabilizing time after release of stp instruction can be selected from ?et automatically??ot set automati- cally?by the oscillation stabilizing time set bit after release of the stp instruction (bit 0 of misrg (address 38 16 )). when ? is set to this bit, ?1 16 ?is set to timer 1 and ?f 16 ?is set to prescaler 1 automatically at the execution of the stp instruc- tion. when ??is set to this bit, set the wait time to timer 1 and prescaler 1 according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. (4) the stp instruction cannot be used when the on-chip oscilla- tor is selected by the clock division ratio selection bits (bits 7 and 6 of cpu mode register (address 3b 16 )). (5) when the stop mode is used, set the on-chip oscillator oscilla- tion control bit (bit 3 of cpu mode register (address 3b 16 )) to ??(on-chip oscillator oscillation stop). (6) do not execute the stp instruction during the a/d conversion. 7544 group rev.1.04 2004.06.08 page 66 of 66 rej03b0012-0104z electric characteristic differences among mask rom and one time prom version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask rom and one time prom version mcus due to the differences in the manufac- turing processes. when manufacturing an application system with one time prom version and then switching to use of the mask rom version, per- form sufficient evaluations for the commercial samples of the mask rom version. note on power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 f to 0.1 f is recommended. one time prom version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin with 1 to 10 k ? resistance. the mask rom version track of cnvss pin has no operational in- terference even if it is connected via a resistor. revision history rev. date description page summary (1/1) 7544 group data sheet 1.00 nov. 8, 2002 1.01 may. 6, 2003 1.02 jun. 25, 2003 1.03 feb. 12, 2004 1.04 jun. 08, 2004 first edition issued added to electrical characteristics entered to limits icc power source current on-chip oscillator operation mode, on-chip oscillator operation mode(in wit state) entered to limits a/d converter characteristics table 2 and fig.6: under development eliminated. [interrupt edge selection register] added. fig.23: ??is added to fig. title and register name. timer count source set register 1, tcss 1 notes on a/d converter added. fig.38: processing of x in pin revised. data required for mask orders added. notes on a/d converter added. table 12: v oh /v ol test conditions revised. hysteresis reset revised. table 14: abs test conditions revised. note added. fig.4 pin configuration : 36pjw-a added. fig.7 functional block diagram: 36pjw-a added. package: 36pjw-a added. table 2: m37544m2-xxxhp, m37544g2hp added. ?nder development?eliminated. fig.14: sio1sts siosts, sio1con siocon fig.23: address revised. fig.25: bit 6 revised. comparator and control circuit revised. oscillation stop detection circuit revised. fig. 46, fig. 47 a bit name revised. countermeasure against noise added. (notes on peripheral functions described previously here are included in appendix at the end of this data sheet.) part number: m37544m2-xxxhp, m37544g2hp added. package outline: 36pjw-a added. appendix added. words standardized: on-chip oscillator, a/d converter 44 to 48 48 49 6 17 23 29 33 38 39 47 49 3 6 8 14 23 25 31 37 38 41 49 58 59 to 66 all pages keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ?2002 , 2004 . re nesas tec hnology corp ., all rights reserved. printed in japan . colophon .1.0 |
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